At t=2.7mS, one clock cycle before the last bit is shifted out of the register, the shift-left control input is asserted (third trace from the top) and the data bit is shifted through the register in the opposite direction. Consequently 3 active-high bits are shifted through the 12 bits of the register at each successive clock interval. Here is screen shot of the complete simulation I have up and running of the shift register: And here it is in operation: At t=1.3mS the serial data input (second trace from the top) goes high for three clock periods. The slaved R-S flop-flop forms a memory element for the data present at the instant of the clock edge. The data-flop flops themselves are reasonably complex each flop-flop consisting of coupled slave and master R-S flop-flop with steering logic to give an edge triggering capability to the clock input that is wholly insensitive to propagation delays. The heart of the register is 12 clocked data-input, edge triggered flop-flops with control and signal steering logic. With the exception of the computers memory, the circuitry is going to be entirely discrete transistor. One of the "building blocks" I am currently working on the the universal bidirectional 12-bit shift register, for the machines accumulator and program counter.
It's going to be a 12-bit machine with 4096 words of 12-bit memory but a reduced version of the PDP-8's instruction set. Most of the logic flow diagrams are also worked out.
I've done a reasonable amount of prototyping on the bench to verify the constructional blocks of the machine and have the complete specification sorted out. In the meanwhile I have been working on an off on the design of the digital machine. My analog computer construction is temporarily on the back burner again as I wait for a batch of PCB's and semiconductors to arrive. In my "Homebrew analog computer" thread I mentioned a couple of times that I am planning to build a work-alike to the PDP-8 digital computer.
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